1. Field of the Invention
The present invention generally relates to methods and apparatus for performing a photoresist development process, a photoresist line width roughness process, a defect control process, and an etching process and, more specifically, to methods and apparatus for performing a photoresist development process, a photoresist line width roughness process, a defect control process, and an etching process in a single chamber in semiconductor processing technologies.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g. to sub-micron dimensions), more elements are required to be put in a given area of a semiconductor integrated circuit. Accordingly, lithography processes have become more and more challenging to transfer even smaller features onto a substrate precisely and accurately without damage. In order to transfer precise and accurate features onto a substrate, a desired high resolution lithography process requires having a suitable light source that may provide a radiation at a desired wavelength range for exposure. Furthermore, the lithography process requires transferring features onto a photoresist layer with minimum photoresist line width roughness (LWR). After all, a defect-free photomask is required to transfer desired features onto the photoresist layer. Recently, an extreme ultraviolet (EUV) radiation source has been utilized to provide short exposure wavelengths so as to provide a further reduced minimum printable size on a substrate. However, at such small dimensions, the roughness of the edges of a photoresist layer has become harder and harder to control.
In a conventional lithography process, some portions of a photoresist layer disposed on a substrate are exposed to incident radiation to undergo a chemical transformation. In a traditional positive tone exposure process, the exposed portion of the photoresist layer experiencing the chemical transformation is removed during development processes with an aqueous base solution. As the feature sizes formed on microelectronic devices continue to shrink, the aqueous base solution developer may become problematic due to image collapse caused by the capillary forces and surface tension of water. Furthermore, solution based developer tends to leave undesired contaminates on the substrate after the development process, thereby adversely effecting the substrate cleanliness.
Furthermore, after the development process, non-smooth edges of developed features also become problematic as feature sizes get smaller. FIG. 1 depicts an exemplary top isometric sectional view of a substrate 100 having a patterned photoresist layer 104 disposed on a target material 102 to be etched after the development process. Openings 106 are defined between the patterned photoresist layer 104 ready to expose the underlying target material 102 for etching to transfer features onto the target material 102. However, inaccurate control or low resolution of the lithography exposure process may cause poor critical dimension control in the photoresist layer 104, thereby resulting in unacceptable LWR 108. Large LWR 108 of the photoresist layer 104 may result in inaccurate feature transfer to the target material 102, thus, eventually leading to device failure and yield loss.
Therefore, there is a need for a method and an apparatus to control process defects during a develop process, and minimize LWR after the development process to obtain a patterned photoresist layer with desired critical dimensions.